Getting to know the NUCLEO — L476RG
STM32 Cortex — M4 implementation
The Cortex-M4 processor is a high performance 32 bit processor designed for microcontroller applications. It’s built with a 3-stage pipeline Harvard architecture.
Features
- High performance
- Fast Interrupt handling
- Enhanced system debug with extensive breakpoint and trace capabilities
- Efficient core, system and memories
- Ultra-low power consumption with integrated sleep modes
- Platform security robustness, With integrated Memory Protection Unit (MPU)
Math related optimizations and hardware
- Includes IEEE754-compliant single-precision floating-point computation
- a range of single-cycle and (Single Instruction Multiple Data) SIMD multiplication and multiply-with-accumulate capabilities.
- Saturating arithmetic and dedicated hardware division.
Integrated debug hardware
- It provides a high visibility of the processor and memory through a JTAG port or a 2-pin Serial Wire Debug (SWD)
- For system trace the processor uses an ITM (Instrumentation Trace Macrocell) alongside data watchpoints and a profiling unit.
- Embedded Trace Macrocell (ETM) provides instruction capture in a small area.
Core peripherals
Nested Vectored Interrupt Controller
- NVIC is an embedded interrupt controller that supports low latency interrupt processing.
System Control Block
- The system control block SCB is the programmer’s model interface to the processor.
System Timer
- 24-bit count down timer. Use this as a Real Time Operating System (RTOS) or a simple counter.
Memory Protection Unit
- improves system reliability by defining memory attributes for different memory regions.
Floating-point unit
- FPU for short, is compliant with the IEEE754 operations with single precision 32 bit floating point values.
Program model
Thread Mode: for application software. Thread mode is activated when it comes out of a reset. The Control register decides whether the execution is privileged or not.
Handler Mode: Used when an exception is met, then it returns to thread mode. The handler execution is always privileged
Unprivileged.- there are some restrictions when code is unprivileged.
- Limited access to MSR, MRS, and CPS instructions, usually used for memory operations.
- Can’t access system timer, NVIC, or system control block
- Restricted access to memory and peripherals
- Must use the SVC instruction to make a supervisor call to transfer
Privileged.- Little to no restrictions on use of instruction, memory access, or peripherals. You can use the control register to tweak the privilege level
The Stack
Processor uses a full descending stack, which means that it points to the last stacked item. There are two stacks used by the processor. The main Stack and the process stack, both with independent copies of the stack pointer.
In thread mode, we can use the control register to set whether we use the main and process stack, in handler mode the main stack is always used.
Core registers
- General purpose registers.- R0 to R12, used to manipulate data or variables
- Stack pointers: Main Stack Pointer (MSP) — Process Stack Pointer (PSP) — both are on R13, Control register determines use.
- Link register LR, register R14, it stores information for subroutines, function calls and exceptions.
- PC program counter.- quite known, used to identify the location in which the current instruction is being executed
- Program status register.- It contains information about flags from interrupts, Negative flag, zero flag, etc.
- Exception mask register: PRIMASK — FAULTMASK — BASEPRI — Masks used to enable/disable the handling of certain exceptions.
- Control Register.- This register controls the stack used and the privilege level for software execution for Thread mode and also is used to define if the FPU state is active.
note: in an OS environment, it is recommended that in Thread mode the process stack is used, and the kernel and exception handlers use the main stack.
Memory model
Memory Access
While coding it is always recommended that the program use the Code region, The reason being that the processor has separate buses that enable code instruction fetches and data accesses to occur simultaneously.
Let’s take a moment to see why the manufacturer’s make that distinction. First let’s remember what an instruction cycle is
Instruction Fetch => Instruction decode => Execute => Memory Access = > Write Back
Usually in a Computer design/architecture class, to learn how a processor is built we use the MIPS as an example. Down below we can see the instruction cycle translated into the 5 stages. Notice that the fetch and memory access are in different stages and execute at different times.
If we look back at the block diagram of the Cortex-M4. The manufacturer’s distinction tells us that the code region bus and the memory access bus are separate allowing us to fetch instructions and accessing memory simultaneously
Memory endianness
endian formats just mean that in a certain structure the when assign the most or least significant byte bases on position. For example, the Cortex-M4 has a little endian format. The least significant byte is stored at the first position.
Exception model
Exception States
Exception Types
Power management & Working modes
Sleep .- This mode stops the processor clock, however other peripherals and clocks may still run.
Wait for interrupt.- the WFI instruction causes an immediate entry to sleep mode
Wait for event.- It checks the value of the event register
- 0: the processor stops executing instructions and enters sleep.
- 1: register clears and continues executing instructions
Sleep-on-exit.- if the SLEEPONEXIT bit of the SCR is set to 1, when the execution of an exception handler, It returns to thread mode and immediately enters sleep mode.
Deep sleep.- stops most clocks and peripherals.
